Vertical semiconductor component with source-down design and corresponding fabrication method

ABSTRACT

The present invention provides a semicond component having a substrate ( 10 ) of a first conduction type (n + ); provided on the substrate ( 10 ) , an optional first Layer ( 20 ) of the second conduction type (p + ) as brody :onnection region; provided on the first layer ( 20 ) or the substrate ( 10 ), a second layer ( 30 ) of the second conduction type (p) as body region; provided on the second layer ( 30 ), a third layer ( 40 ) of the first conduction oype (n) as drain region; a trench ( 140 ) reaching down to the substrate ( 10 ); a gate structure ( 90, 100 ) provided in the trench ( 140 ); and a source region ( 130 ) of the first conduction type (n + ), said ,carce region being provided in the second layer (30) in the periphery of the trench (140); the source region ( 130 ) being short-circuited with the first layer ( 20 ) and the substrate ( 10 ) by a conductive layer ( 120 ) provided in the lower region of the trench.

DESCRIPTION

[0001] The present invention relates to a vertical semiconductorcomponent with source-down design and a corresponding fabricationmethod.

[0002] DE 196 38 439 Al discloses a field effect-controllable, verticalsemiconductor component, comprsing a semiconductor body with at leastone drain region of the first conduction type, at least one sourceregion of the first conduction type, at least one body region of thesecond conduction type between drain region and source region, and atleast one gate electode which is insula ed from the entire semiconductorbody by a gate oxide, the gate terminal and drain terminal beingsituated on the front side of the wafer and the source terminal beingsituated on the rear ide oe the wager.

[0003] Although applicable to any semiconductor components, he presentinvention and the problems on which it is based will be explained withregard to vertiial source-dcwn power transistors.

[0004] Source-down power transistors in the form of individual switchesand in the form of integrated multiple switches (with commonsource=common source terminal) afford advantages of a circuitry andthermal nature.

[0005] One problem in their fabrication is that the source region andthe body region, which are buried in the silicon, must beshort-circuited to ensure that the parasLtic bipolar transistor does notswitch on.

[0006] It is an object of the present invention, therefore, to provide asemiconductor component of the type mentioned in the introduction inwhich the short circuit between source region and body region can befabricated favorably in terms of process engineering. A further objectis to provide a corresponding fabrication method.

[0007] According to the invention, this object is achieved by means ofthe semiconductor component specified in claim 1 and, respectively, bymeans of the Fabrication method specified in claim 6.

[0008] The idea underlying the present invention consists in realizingthe semiconductor component as a trench component, the trench containingthe gate electrode. The short circuit between body region and sourceregion is realized in the lower region of the trench, in which case,instead of the substrate, an additional, preferably implanted regionserves as source region which is short-circuited with the substrate andthe body region, for example via a silicide.

[0009] In this case, it is expedient to provide a process sequence whichproduces insulation of the gate from the short circuit between bodyregion and source region and also thicker insulation in the upper partof the tranch with respect to the insulation between drain and gate.

[0010] One advantage of the configuration according to the invention isthat the short circuit between body region and source region is realizedin a space-saving manner in the lower region of the trench.

[0011] Advantageous developments and improvements of the semiconductorcomponent specified in claim 1 and, respectively, of the fabricationmethod specified in claim 6 may be found in the subclaims.

[0012] In accordance with a preferred development, at least one of thefirst, second and third layers (20, 30, 40 is an epitaxial layer.

[0013] In accordance with a further preferred oevelopment, the sourceregion (130) is an implantation region

[0014] In accordance with a further preferred developement, theconductive layer (120) is a silicide layer.

[0015] In accordance with a further preferred development, the silicidelayer is produced by cepositing a metal, preferably tungsten, in thetrench anrd thermal siliciding.

[0016] In accordance with a further preferred development, the firstconduction type is the n conduction type.

[0017] In accordance with a further preferred development, the secondlayer (30) is formed by implantation into the bottom of the trench andoutdiffsion prior to the source implantation.

[0018] Exemplaary embodiments of the invention are illustrated in thedrawings and explained in more detail in the description below.

[0019] In the figures:

[0020]FIG. 1 shows a schematic illustration of a semiconductor componentas an embodiment of the present invention; and FIG. 2 a-e show aschematic illustration of the essential method steps for fabricating thesemiconductor component according to FIG. 1.

[0021] In the figures, identical reference symbols designate identicalor functionally identical elements.

[0022]FIG. 1 is a schematic illustration of a semiconductor component asan embodiment of the present invention.

[0023] In FIG. 1, 10 designates an n⁺-type substrate, 20 designates ap⁺-type epitaxial layer (body terminal), 30 designates a p-typeepitaxial layer (body), 40 designates an n-type epitaxial layer (drain),50 designates a drain terminal, 60 designates an insuilation region, 70designates a drain contact, 80 designations a first insulation layer, 90designates a gate, 100 designates a gate oxide, 110 designates a secondinsulation layer, 120 designates a silicide region, 130 designates asource region and 140 designates a trench.

[0024] This embodiment 5 a source-down power transistor with a substrateof the n⁺conduction type.

[0025] A first, second and third epitaxial layer 20, 3C, 40 are providedon then^(+ -type substrate 10, namely the firet laver 20 of the p conduction type on the substrate 10 as body terminal region, the second layer 3C of the p conduction type on the first layer 20 as body region, and the third layer 40 of the n conduction type on he second layer 30 as drain region.)

[0026] The trench 140 reaching down to the substrate 10 contains a gatestructure 90, 100 with a gate 90 and a gate oxide 100, the gate 100being insulated from its surroundings by the insulation layers 90 and110 and also the insulation region 60.

[0027] The source region 130 of then^(+ conduction type, which is an implantation region, is provided in he second layer 30 in the periphery of the trench 140. The soure region 130 is short-circuited with the first layer 20 and the substrate 10 by a conductive layer 120 in the form oa a silicde layer provided in the lower region of the trench.)

[0028]FIG. 1 shows two such transistors, the right-hand transistorhaving a gate 90 which is connected or wired toward the outside to theright, and the leftc5 hand transistor having a gate 90 which isconnected or wired toward the back (third dimension) by a transversetrench (not illustrated).

[0029]FIGS. 2a-f are schematic illustrations of the essentIal methodsteps for fabricating the is0 semicondIctor component according to FIG.1.

[0030] In accordance with FIG. 2a, the n⁺-type substrate 10 is provided,and then the following are Arm ed eoitaxiallv: the first layer 20 of theconduction type p⁺on the substrate 10, the second layer 30 of theconduction type p on the first layer 20, and the third layer 40 of theconduction type n on the second layer 30.

[0031] On top of this an oxide 45 is deposited and a trench 140 isformed, said trench reaching down to the second layer 20. The latterprocess fs performed by forming a phoomask on the oxide 45 andanisotropically etching the oxide 45 (hard mask) and the trench. Ascreen oxide 48 is subsequentlv formed in the trench 140. Afterward, thesource region 130 of the conduction type n⁺is implanted and diffused inthe lower part of the second layer 30 in the periphery of the trench140.

[0032] By means of further anisotropic etching, the trench 140 is thendeepened down to the substrate 10, as illustrated in FIG. 2b.

[0033] The next step is that, in accordance with FIG. 2c, the sourceregion 130 is short-circuited with. the first layer 20 and the substrate10 by forming the ccnductive layer 120 in the lower region of thetrench. For this purpose, a metal, e.g. tungsten, is formed by conformaldeposition in the trench and, in the loser region where it lies on thesilicon (that is to say below the remaining screen oxide 48), isconverted into the conductive layer 120 made of silicide by means of athermal reaction. The residual metal situated on oxide is removed bysubsequent etching.

[0034] In accordance with FIG. 2d, oxide 110 is then ideposited, anauxiliary layer 55 is applied, and the auxiliary layer 55 is etchedback.

[0035] As shown in FIG. 2e, the oxide 110 is etched in the region abovethe remaining auxiliary layer 55 and a gate oxide 100 is formed. Theauxiliary layer 55 is then removed and gate polysilicon is depositedover the resulting structure. The gate polysilicon is doped, ifappropriate, and then etched back.

[0036] Then, if necessary for insulation purposes, a thicker oxide 80 isformed analogously to the oxide 110 in the upper region of the trench,thermally or by deposition.

[0037] In order to arrive at the structure of FIG. 1, the oxide 80 isthen etched anisotropically in order to remove it from the top side ofthe gate polysilicon 90, and renewed deposition, doping and etching-backof further gaL polysilicon 90 then take place. Finally, the insulationregion 60 is formed on the top side of the trench using borophosphorussilicate glass (BPSG). Using a mask, contact holes for the drainterminal are formed and the drain contact 70 is implanted in aselfalignLng aligning manner. Finally, the metal plane for the draintermimal 50 is formed in order to complete the transistor.

[0038] Although the present invention has been described above usingpreferred exemplary embodiments, it is not restricted thereto but rathercan be modified in diverse ways.

[0039] In particular, in a further preferred embodiment, the body is notrealized by an epitaxial layer but by p-type implantation into thebottom of the trench and outdiffusLon prior to the source implantation.

[0040] Moreover, The present invention is not restricted to thetransistor portrayed, but rather can be applied to some other morecomplicated structure, e.g. a thyristor structure.

[0041] Furthermore, the body terminal region is not absolutelynecessary, rather it is also possible to connect the body regiondirectly.

1. A semiconductor component having: a substrate (10) of a firstconduction type (n⁺); provided on the substrate (10), an optional firstlayer (20) of the second conduction type (p⁺) as body connection region;proviced on the first layer (20) or the substrate (10), a second layer(30) of the second conduction type (p) as body region; provided on thesecond layer (30), a third layer (40) of the first conduction type (n)as drain region; a trerch (140) reaching down to the substrate (10); agate structure (90, 100) provided in the trench (140); and a sourceregion (130) of the first conduction type (n⁺), said source region beingprovided in the second layer (30) in the periphery of the trench (140);the source region (130) being short-circuited with the first layer (20)and the substrate (10) by a conductive layer (120) provided in the lowerregion of the trench.
 2. The semiconductor component as claimed in claim1, characterized in that at least one of the first, second and thirdlayers (20, 30, 40) is an epitaxial layer:
 3. The semiconductor omponentas claimed in claim 1 or 2, characterized in that the source region(130) is an implantation region.
 4. The semiconductor component asclaimed in one of the preceding claims, characterized that theconductive layer (120) is a silicide layer.
 5. The semiconductorcomponen as claimed in one of the preceding claims, characterized inthat the first conduction type is the n conduction type.
 6. A method forfabricating a semiconductor component having the steps of: provicing asubstrate (10) of a first conduction type optionally providing a firstlayer (20) of the second conduction type (p+) on the substrate (10);providing a second layer (30) of the second conduction type (p) on thefirst layer (20) or the substrate (10); providing a third layer (40) ofthe first conduction type (n) on the second layer (30); forming a trench(140) reaching down to the second layer (20); forming a source region(130) of the first conduction type (n⁺) in the lower part of the secondlayer (30) in the periphery of the trench (140); deepening the trench(140) down to the substrate (10); short-circuiting the source region(130) with the first layer (20) and the substrate (10) by forming aconductive layer (120) in the lower region of the trench; and forming agate structure (90, 100) in the trench (140).
 7. The method as claimedin claim 6, characterized in that the first, second and third layers(20, 30, 40) are deposited epitaxially.
 8. The method as laimed in claim6 or 7, characterized in that the source region (130) is ion-implanted.9. The method as claimed in one of the preceding claims 6 to 8,characterized in that the conductive layer (120) is a silicide layerproduced by depositing a metal, eferably tungsten, in the trench (140)and thermal siliciding.
 10. The method as claimed in one of thepreceding claims 6 to 9, characterized in that first conducion type isthe n conduction type.
 11. The method as claimed in one of the precedingclaims 6 to 9, charactterized in that the second layer (30) is formed byimplantation into the bottom of the trench and outdiffusion prior to thesource implantation.